1. Field of the Invention
The present invention provides a voltage level shifting module, and more particularly, a two-stage voltage level shifting module utilized on a plurality of I/O devices having different bias voltages.
2. Description of the Prior Art
With the growth of integrated circuits and in the fabrication procedure of the integrated circuits, the areas and volumes of the integrated circuits are decreased. Therefore, a bias voltage applied on an integrated circuit is decreased in accordance to the decreased volume of the integrated circuit. Under such a circumstance, it is more popular to drive and connect an integrated circuit having a lower bias voltage with external devices having higher bias voltages. However, the external devices are not decreased in their bias voltages with the evolvement of the integrated circuit, or are not able to follow the velocity of decreasing the bias voltage of the integrated circuit. External devices of this kind include conventional Input/Output (I/O) devices. As mentioned above, it cannot be smoothly operated in directly driving and connecting an integrated circuit having a lower bias voltage with external devices having higher bias voltages. For neutralizing such drawbacks, a voltage level shifting circuit is further added on the integrated circuit in the prior art for raising the lower bias voltage of the integrated circuit to match the external devices having the higher bias voltages.
However, new problems arise along with the added voltage level shifting circuit. First, because of the continuously decreased volume of an integrated circuit in related fabrication procedure, thicknesses of metal oxide semiconductor field-effect transistors (MOSFET) are decreased so that upper bounds of the voltage levels at the gates of the MOSFETs are gradually decreased as well, whereas a voltage level, which is at the gate of a MOSFET and is higher than the upper bound, leads to the gate oxide breakdown of the MOSFET. Moreover, the abovementioned voltage level shifting circuit just raises an upper bound of a bias voltage range of the integrated circuit in fact, whereas the lower bound of the bias voltage range is kept. In other words, merely a voltage level indicating the digital logic 1 is raised, whereas a voltage level indicating the digital logic 0 is kept. For example, a bias voltage range of an integrated circuit is assumed to be raised from 0-1.8 volts to 0-3.3 volts, where the voltage level indicating the digital logic 1 is raised from 1.8 volts to 3.3 volts for matching bias voltages of external devices, and the voltage level indicating the digital logic 0 is 0 volts. However, when the bias voltage range of the integrated circuit is broadened, a voltage difference between voltage levels of a gate and a source of each MOSFET of the integrated circuit easily leads to the gate oxide breakdown of each MOSFET, and brings permanent damage to each MOSFET as well. It can be observed that the method of adding a voltage level shifting circuit inside an integrated circuit in the prior art has to be improved. For a MOSFET under the 0.18 μm fabrication procedure, a voltage difference of 3.3 volts easily leads to the gate oxide breakdown.
Please refer to FIG. 1, which is a diagram of a voltage level shifting circuit 100 capable of increasing an upper bound of a bias voltage range in the prior art. As shown in FIG. 1, the voltage level shifting circuit 100 includes an invert logical operational amplifier 102, a first N-type MOSFET 104, a second N-type MOSFET 106, a third N-type MOSFET 108, a fourth N-type MOSFET 110, a first P-type MOSFET 112, and a second P-type MOSFET 114. The invert logic operational amplifier 102 has a positive bias terminal coupled to a voltage source VDD1, and a negative bias terminal coupled to ground, an input terminal coupled to a signal source Input. A voltage level of the signal source Input is between the voltage levels of the voltage source VDD1 and ground. The first N-type MOSFET 104 has a gate coupled to an output terminal of the invert logic operational amplifier 102, and a source coupled to ground. The second N-type MOSFET 106 has a gate coupled to the signal source Input, and a source coupled to ground. The third N-type MOSFET 108 has a source coupled to a drain of the first N-type MOSFET 104, and a gate coupled to a voltage source VDD2. A voltage level of the voltage source VDD2 is higher than the voltage level of the voltage source VDD1. The fourth N-type MOSFET 110 has a source coupled to a drain of the second N-type MOSFET 106, and a gate coupled to the gate of the third N-type MOSFET 108. The first P-type MOSFET 112 has a drain coupled to a drain of the third N-type MOSFET 108, a gate coupled to a drain of the fourth N-type MOSFET 110, and a source coupled to a voltage source VDDIO. A voltage level of the voltage source VDDIO is higher than the voltage level of the voltage source VDD2. The second P-type MOSFET 114 has a drain coupled to the drain of the fourth N-type MOSFET 110, a gate coupled to the drain of the third N-type MOSFET 108, and a source coupled to the voltage source VDDIO.
The voltage level shifting circuit 100 is primarily utilized for broadening the voltage range of the signal source Input by raising an upper bound of said voltage range. While describing operations of the voltage level shifting circuit 100 in FIG. 1, the following assumptions are made and include (a) the voltage level of the voltage source VDD1 is 1.0 volts, (b) the voltage level of the voltage source VDD2 is 2.5 volts, (c) the voltage level of the voltage source VDDIO is 3.3 volts, and (d) the voltage range of the signal source Input is between 0 and 1.0 volts for indicating digital logic 0 and 1 respectively. The invert logic operational amplifier 102 is biased between ground (with 0 volts) and the voltage source VDD1 so that a voltage level of an output voltage of the invert logic operational amplifier 102 may be fully raised to 1.0 volts or fully decreased to 0 volts. The invert logic operational amplifier 102 may be implemented by coupling a conventional operational amplifier to an inverter so that a voltage having a high voltage level may be fully transformed into another voltage having a low voltage level, and vice versa, where it is a conventional method of clearly differentiating a low voltage level from a high voltage level and is not be discussed further. Operations of the voltage level shifting circuit 100 are described as follows. When a signal of the signal source Input indicates the digital logic 1, a voltage level at the gate of the first N-type MOSFET 104 is low, a voltage level at the gate of the second N-type MOSFET 106 is high. Therefore, the first N-type MOSFET 104 is switched off whereas the second N-type MOSFET is switched on. Since the voltage source VDD2 is coupled to both the gates of the third N-type MOSFET 108 and the fourth N-type MOSFET 110, both the third N-type MOSFET 108 and the fourth N-type MOSFET 110 are continuously switched on, and moreover, with the biasing of the voltage source VDD2, voltage levels at the drains of both the third N-type MOSFET 108 and the fourth N-type MOSFET 110 are raised for achieving broadening the voltage range as a purpose at a first level. At the same time, since the first N-type MOSFET 104 is switched off, no current flows through both the first N-type MOSFET 104 and the third N-type MOSFET 108, and a voltage level at the drain of the first P-type MOSFET 112, i.e., the node A+ shown in FIG. 1, is slightly lower than the voltage level of the voltage source VDDIO. Similarly, since the second N-type MOSFET 106 is switched on, there is a current flowing through both the second N-type MOSFET 106 and the fourth N-type MOSFET 110, and a voltage level at the drain of the second P-type MOSFET 114, i.e., the node B+ shown in FIG. 1, is significantly decreased. Note that both output terminals of the voltage level shifting circuit 100 lie at the nodes A+ and B+, and in other words, a voltage difference between the nodes A+ and B+ just indicates the output voltage range of the voltage level shifting circuit 100. Moreover, by biasing of the voltage source VDDIO coupled to sources of both the first P-type MOSFET 112 and the second P-type MOSFET 114, a voltage range, which is previously between voltage levels of ground and the voltage source VDD1, is broadened to be between voltage levels of ground and the voltage source VDDIO. Under the above-made assumptions, the voltage range is broadened from 0-1.0 volts to 0-3.3 volts. However, concerning the gate oxide breakdown, when one of the first P-type MOSFET 112 and the second P-type MOSFET 114 has a source voltage level equal to 3.3 volts and a gate voltage level equal to 0 volts, i.e., when a voltage difference equal to 3.3 volts is generated, the gate oxide breakdown is likely to happen so that permanent damage occurred on the P-type MOSFET, and voltage levels at both the nodes A+ and B+ cannot clearly tell digital logic 0 and digital logic 1.
In the prior art, a method of coupling two same voltage level shifting circuits is also provided for providing a safer and broader voltage range. However, in such a method, since an amount of utilized masks in the integrated circuit must be increased to be at least twice, the capital of fabricating the integrated circuit is increased, and the volume of the integrated circuit is significantly increased as well.